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Land area
That portion of the package lead which is inside the package cavity and to which the bonding wire will be connected to make electrical contact with the die.
A process to remove controlled amounts of silicon from a wafer using a slurry. This process removes saw damage and positively impacts the wafer flatness.
Lap presort
The process whereby slices are inspected for defects and sorted into thickness groups going to Lapping, so that wafers of the same thickness will be lapped together.
Large scale integration(LSI)
The placement of between 100 and 1000 active devices on a single die.
Latch up
A condition where the output of a circuit has become fixed near one of the two voltage extremes and will no longer react to changes in the input signal. Latchup may be radiation induced, but can also result from voltage over stresses and other causes.
Lateral diffusion
Diffusion parallel to the wafer surface. Lateral diffusion of metal-oxide semiconductor source/drain regions determines the effective channel length of the device.
Lateral straggle
The motion of ions parallel to the wafer surface as a result of ion implantation.
The body is made from layers of ceramic or metallized ceramic. The layers are defined by their functionality, and several ceramic layers may be (for example, die attach cavity). Also see package and ceramic chip carrier.
Lead on Chip
Lightly doped drain.
Lead fatigue
Application of a repetitive bending force to the leads of sample devices to insure structural integrity of leads and packages.
Lead frame
Sheet metal framework upon which an integrated circuit is attached, wirebonded, and transfer molded with epoxy.
LED(Light Emitting Diode)
A semiconductor device in which the energy of minority carriers in combining with holes is converted to light. Usually, but not necessarily, constructed as a P/N junction device.
Lid torque
A test which tests the integrity of the seal of a semiconductor device (usually one that employs a glass frit seal) by twisting the package and the lid in opposite but parallel directions.
Light point defects
See sparkles.
Lightly doped drain (LDD)
A metal-oxide semiconductor(MOS) device design in which the drain doping is reduced to improve breakdown voltage.
A low angle grain boundary resulting from an array of dislocations. The difference in orientation across the grain boundary may vary from a fraction of a second to a minute of arc. The array of dislocations appears as a row of dislocation etch pits on a preferentially etched surface. Linear arrays of etch pits less than 0.5 mm in length are not considered lineage.
The closeness to which a curve approximates a straight line. It is measured as a no linearity and expressed as a linearity.
The transfer of a pattern or image from one medium to another, as from a mask to a wafer.
localized light scatterer.
Localized light scatterer(LLS)
An isolated feature, such as a particle or pit, on or in a wafer surface, resulting in increased light scattering intensity relative to that of the surrounding wafer surface. Also called. Contrast point defect.
The circuits used to control operations of IC devices.
Abbreviation for light point defect. See localized light scatterer.
See latex sphere equivalent.
Large Scale Integration - LSI devices are generally accepted to be those that contain between 100 and 1000 gate equivalents, or other circuitry of similar complexity. (See VLSI.)
Lot Tolerance Percent Defective - A single lot sampling concept that statistically ensures rejection of 90% of all lots having a greater percent defective than the specified LTPD
residual surface contamination deposited on a photomask or photoplate during handling
Resolution dagger
A photolithography tool used to enhance and refine resolution.
A quartz structure with which quartz carriers that contain wafers are moved into, and out of, a furnace.
Process-induced defect
PID. defect(s) added to the wafer as a result of a processing step. The PID wafer undergoes the same process sequence as a product wafer. PID wafer data is a closer approximation of actual process defect contributions than particles per wafer pass (PWP) wafer data.
Polycrystalline silicon
a nonporous form of silicon made up of randomly oriented crystallites or domains, including glassy or amorphous silicon layers. [ASTM F399-88] 2: silicon formed by chemical vapor deposition from a silicon source gas or other methods and having a structure that contains large-angle grain boundaries, twin boundaries, or both. [SEMI M16-89] Contrast amorphous silicon and single crystal.