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An object-oriented programming language developed at AT&T Bell Laboratories during the early 1980s. C++ is a "hybrid" language in which object-oriented features have been grafted onto an existing language.
Calcium scaling
The deposition from water of calcium on a metal surface such as a cooling tube or boiler.
A standard unit of heat equal to the amount of heat required to raise one gram of water one degree Celsius.
Computer Aided Manufacturing. The use of computer automation for all or a portion of the assembly process for a product
Edgewise curvature of a lead frame strip edge in the major plane of the lead frame strip.
Candidate device
A term used to designate a device which has been or will be subjected to a specified test or screening flow but has not yet successfully completed that testing
Cantilever probes
Electrical probes for making contact to bare chips that are constructed with the contact pad at the end of a flexible beam.
Of a ceramic semiconductor package, the top portion, or lid. The cap is attached to the base. Also see package and base.
Capability index
A measure of the relationship between the specification limits and the process capability. Also see process capability index
Capacitance-to-voltage(CV) plotter
An electronic test system used to measure capacitance as a function of voltage between a conductive field plate insulated from a silicon wafer by a dielectric; for example, aluminum or doped silicon insulated from the wafer by silicon dioxide.
Capacitive decoupling
Protection of a device from voltage transients or : spikes", or the isolation of a device from an AC voltage by decoupling the voltage source(s) to ground through a capacitor.
Capacitive load
A load in which the capacitive reactance exceeds the inductive reactance; the load draws a leading current.
The property of a circuit element that permits it to store an electrical charge.
Circular plates onto which wafers are mounted in preparation for the polishing operation, or thin metal sheets with slice-sized holes cut into them to hold slices during the lapping operation.
Computer Aided Test Engineering. The use of computer automation for preparation of electronic test program.
To entrain undesirable elements, such as gases, fumes, vapors, and particles, in the exhaust stream for removalbecause of lack of oxygen in the blood.)
1. An entity capable of carrying electric charge through a solid; for example, mobile holes and condition electrons in semiconductors. Also called Also see majority carrier and minority carrier.
2. Slang for wafer carrier.
Carrier area
The area that includes the angle(in degrees) from the intersection of the horizontal center line of the wafers to the top side members on the right side and on the left side. Also see wafer carrier.
Carrier capacity
The number of wafers a wafer carrier can hold.
Carrier concentration
The number of majority carriers per unit volume, expressed in dimensionless units such as percentage, parts per million, or parts per billion. Also see carrier density
Cascade rinse
A deionized water rinse system in which water flows over the top of a tank.
Case temperature
The temperature at a specified, accessible reference point on the package in which a semiconductor die is mounted. Also see package
An open structure the holds on or more substrates
Cassette stage
A stage on a piece of equipment on which a cassette is placed or from which it is removed, allowing the transfer of the cassette.
Cassette transfer robot
A robot that transfers cassettes.
That series or fibs and metallized indentations that defines edge-contact regions. Also see ceramic chip carrier.
An abnormal progressive condition of the lens of the eye characterized by loss or transparency.
An ion that has a positive charge.
Cation-exchange resin
An ion-exchange resin capable of the reversible exchange of positively charged ions.
Cause-and-effect diagram
A tool for individual or group problem-solving that uses a graphic description of the various process elements to analyze potential sources of process variation.
Describes a substance capable of destroying or eroding by chemical action.
1. The area that is designate for die attach. The nominal area is defined by the limits of the bond finger ledge(or wire bond cavity). Also see effective die attach area.
2. The overall area for wire bonds in a cofired ceramic package.
3. The areas of the mold that become filled with plastic during the molding cycle, encapsulate the die, and form the body of the device. A mold has matching upper and lower cavities, and the term is also used to describe the top or bottom or a finished plastic package.
4. A vacancy or empty space in a wafer. A cavity usually is left by dissolved precipitates or gallium inclusions or by arsenic dissociation, or it may be created by excessive vapor pressure.
5. An unfilled space between the photo mask and the optically transparent film within the mounted pellicle frame area. Also see pellicle and photo masking
Cavity device
A semiconductor device containing an internal cavity (as opposed to a modeled device).
Cavity-down packages
Packages on which the die surface faces the mounting board.
Cavity-to-frame offset
See offset
Cavity length
The length of the lead frame area that will contain the die. The cavity is measured from the ends of the lead tips. Also see package and lead frame.
Cavity-up packages
Packages on which the die surface faces away from the mounting board.
Cavity width
The width of the lead frame area that will contain the die. The cavity is measured from the ends of the lead tips. Also see package and lead frame.
An attributes chart used to track the number of nonconformities with a constant sample size. For example, a C-chart can be used to track the total number of particles per wafer, assuming the underlying particle distribution is a Poisson distribution. See Poisson distribution.
See critical dimension
The concentration that should not be exceeded during any part of the working exposure
A tiny area within the memory array that actually stores the bit in the form of an electrical charge.
Cell array
An integrated circuit formed through the positioning and interconnection of a number of functional blocks, or cells, on a die.
Cell center point
The point in an array at which the center line of a row intersects the center line of a column.
Centralized processing
In digital data systems, a system which utilizes a single large processor, normally in multiprocessing or multiprogramming modes, to perform all required system computations.
See Constant acceleration
Certificate of conformance
A certificate provided by a manufacturer's QA department to the procuring activity with a lot of material to confirm that all material in the lot conforms with all applicable specifications.
Change control
See Configuration control
A region of surface conduction opposite in type from that expected from the bulk doping. Channels are sometimes introduced unintentionally by surface ionic contamination. The type of channel (P or N) will be determined by the type of majority carrier introduced into the channel.
Electrical testing performed for the purpose of determining typical device performance characteristics and/or parametric limits.
A specific amount of silicon (raw, remelt, or a combination) that is to be loaded into a furnace, i.e.,100,000 grams, 120 kilograms, etc.
Charge Carrier
A carrier of electrical charge within the crystal of a solid state device, such as an electron or a hole.
Chemical etch
The dissolution of the material of a surface by subjection to the corrosive action of a liquid or gaseous acid or an alkali.
1. in semiconductor wafers, a region where material has been unintentionally removed from the surface or edge of the wafer.
2. see die.
3. in packaging, a region of material missing from a component; for example, ceramic from a package or solder from a preform. The region does not progress completely through the component and is formed after the component is manufactured. The chip size is given by its length, width, and depth from a projection of the design plan-form.
4. in flat panel display substrates, a region of material missing from the edge of the glass substrate, which is sometimes caused by breakage or handling.
Chip carrier
A leadless package used in the construction of both hybrids and boards. The chip carrier has a body configuration similar to a flat pack, but electrical connection is made through contacts in the package base rather than through conventional leads.
1. A method of separating and analyzing mixtures of chemicals.
2. The separation, especially of closely related compounds, by allowing a solution or mixture to seep through an adsorbent (such as clay, gel, or paper) so each compound becomes adsorbed into a separate, often colored, layer.
Chuck mark
Any physical mark on either surface of a wafer caused by a robot end effectors, a chuck, or a wand.
The combination of a number of connected electrical elements or parts to accomplish a desired function.
Circuit geometries
The relative shapes and sizes of features on a die.
Class (electrical classification testing)
Post assembly 100% electrical sort testing, not to be confused with the product assurance classes.
Class (product assurance class)
There are two product assurance classes representing different levels of anticipated device reliability: Class B, which is intended for airborne equipment; and Class S, which is intended for space flight.
Class 10, 100, etc
See particle count
Clean room
The super-clean environment in which wafers and semiconductors are manufactured. These rooms typically have hundreds of thousands of particles less per cubic foot than the normal environment. The smaller the "class," (i.e. Class 10,000, Class 1000, Class 100 or Class 1), the cleaner the facility.
An object that uses the functionality defined by another object(the server) to implement a certain portion of its own functionality. In this sense, a client delegates responsibility to the server.
A function that provides time stamping of event reports and alarm messages. The clock allows the equipment to be instructed by the host to set an internal clock to a time value specified by the host. The equipment can request the current date and time.
Clock frequency
The master frequency of the periodic pulses that synchronize oprations of a logic circuit.
Complementary Metal Oxide Semiconductor. A MOS device containing both N-channel and P-channel MOS active elements. One of two basic processes (MOS and Bipolar) used to fabricate integrated circuits.
Chemical Mechanical Polishing. A technique that removes defects and globally planarizes silicon wafers.
1. To cover a substrate surface with a layer of a material by the spinning of a resist.
2. The cover applied by the spinning of a resist.
3. A step in the resist-apply operation in which a uniform film is applied to the entire face of a wafer.
Coefficient of thermal expansion
The increase in length or volume of a solid, liquid, or gas for a rise of 1 degree C at constant pressure. This coefficient is used, along with the glass transition temperature, to determine the expansion characteristics of molding compounds used in the manufacture of semiconductor packages. Usually, the linear coefficient is used for packaging considerations
Complex hybrid
A hybrid having an inner seal perimeter (that is cavity perimeter) of greater than 2 inches
Compound bond
In hybrid, the monometallic bonding of one band on top of another.
The relative amount of a minority constituent of a mixture to the majority constituent(in, for example, parts per million, parts per billion or percentage) by either volume or weight.
Conductivity, electrical
A measure of the ease with which charge carriers flow in a material; the reciprocal of Also see carrier
A substance through which electricity can readily flow. Contrast insulator.
Confidence interval (CI)
Upper and lower bounds around an expected value that will, within a certain percentage of confidence, include the expected value.
The definition of equipment and interfaces necessary for a given application.
Configuration control
A requirement that a vendor notify the procuring and/or qualifying activity of a change in product manufacture or test. In some cases, the requirement will include delay of change implementation until after formal approval of the change.
To be similar in form and character and to behave in accordance with prevailing modes or customs.
Conformal coating
Thin, nonconductive film applied to a circuit for environmental or mechanical protection; usually plastic or inorganic.
Conjugate bridge
The detector circuit and the supply circuit are interchanged as compared with a normal bridge of the given type.
Connected tubs
Adjacent tubs that are not completely surrounded by an oxide but are connected by silicon.
The capability of forming an operative data link between two units.
Constant temperature oven
A hot-air oven used to condition the specimens to the specified temperature.
1. Categories of information used to define something.
2. The language from which a model is created and specified.
An opening that allows electrical connection between metal and silicon layers. Also see window and via.
1. An unwanted substance present in the clean room or on the product. Also see dirt and particulate.
2. Surface feature that cannot be removed by the pre inspection (non etching) cleaning.
A broad category of foreign matter visible to the unaided eye on the wafer surface. In most cases, it is removable by gas blow off, detergent wash, or chemical action. See also particulate contamination, stain.
Contamination free manufacturing
Integrated circuit processing without adding contaminants that degrade the electrical performance of a finished die.
Control chart
A graphic representation of a characteristic of a process that shows plotted values of statistical data gathered from that characteristic, a central line, and one or two statistically derived control limits.
Control limits
The maximum allowable variation of a process characteristic as a result of common cause alone. Calculated from process data and usually represented as a line(or lines) on a control chart. Not to be confused with engineering specification limits.
Convection oven
An electric oven used for baking and removing moisture from wafers. The heat is transferred by air flow, rather than by direct contact or radiation.
See cost of ownership
A processing unit that performs specific funtions delegated by the main processor in a computer system. Examples are the graphics coprocessor and the floating point coprocessor.
1 : a region of a crystal that has different characteristics from the rest of the crystal, usually higher dopant density.
2 : on a polished monocrystalline gadolinium gallium garnet wafer, a material defect caused by nonplanar growth interface. This defect normally is highly stained and misoriented with respect to the surrounding area.
Cost of ownership(COO)
The total lifetime cost associated with acquisition, installation, and operation of fabrication equipment.
Cost/resource model(CRM)
A factory level model developed by SEMATECH that can estimate total fab, assembly, and test cost. It can mo multiple products using multiple processes. Based on a business plan, it performs factory sizing and reports product costs. CRM can perform four types of analyses: step yield modeling, resource planning, product costing, and financial feasibility.
See process capability
Central Processing Unit. The computer module in charge of retrieving, decoding, and executing instructions.
Cleavage that extends to the surface of a wafer and which may or may not pass through the entire thickness of the wafer. Also known as fissure ; see also fracture.
Structures with parallel major axes, attributed to substrate defects either above or below the surface plane of silicon substrates after epitaxial deposition.
Critical dimension(CD)
The width of a patterned line or the distance between two lines, monitored to maintain device performance consistency; that dimension of a specified geometry that must be within design tolerances.
Critical path
The longest sequence of interdependent activities. The delay of any critical path activity will cause a corresponding delay in completion of the project.
Critical temperature
The temperature above which gas cannot be liquefied by pressure alone.
General term meaning to cut off a section of a crystal with a diamond-edge saw. Examples are cropping nose, tail, structure loss, under-diameter section, etc.,; not to be confused with slicing
The structure that connects the two sides of a wafer carrier at the bar end of the carrier and is used to align the carrier to processing equipment. Also called a bar or an H-bar.
The transverse bowing of a lead frame strip. Contrast coil set. Also see package and lead frame.
Crow's foot
Intersecting cracks in a pattern resembling a "crow's foot" (Y) on {111} surfaces and a cross (+) on {100} surfaces.
A bowl made of either transparent or opaque quartz and used to hold the raw silicon ; comes in several sizes, i.e., 10"X7.5"(10" in diameter by 7.5" deep), 12"X7.5", etc.
A solid composed of atoms, ions, or molecules arranged in a pattern that is periodic in three dimensions.
Crystal defect
Departure from the regular arrangement of atoms in the ideal crystal lattice.
Crystal growing
The process whereby a crystal is formed by pulling and cooling molten silicon into a specific shape and structure.
Crystal lattice
The three dimensional and repeating pattern of atoms.
Crystallographic notation
A symbolism based on Miller indices used to label planes and directions in a crystal as follows;
(111) plane
[111] direction
{111} family of planes
<111> family of directions
Crystal orientation
The crystallographic axis, described in terms of its Miller indices, on which the silicon crystal in grown. Commercial silicon is generally supplied in [100] or [111] orientations.
Crystal originated particle(COP)
A surface depression that is formed during soft alkaline chemical treatment of silicon wafer surfaces that contain crystal defects at or close to the wafer surface and that scatters light similarly to a very small particle. Also called surface micro defect.
Customer Specific Integrated Circuit. An integrated circuit designed for one specific application for one customer. With the growth of semi-custom devices, such as gate arrays, this term has been discarded in favor of ASIC.
Current carrying edge
That portion of metal over a contact window that is closest to the point at with the metallization stripe enters the contact window.
Chemical vapor deposition. A process in which a controlled chemical reaction produces a thin surface film. Contrast physical vapor deposition.
C-V plotter
See capacitance-to-voltage (CV) plotter
Backside abrasion
A process whereby the backside of a finished wafer is cleaned using a fine-granular powder under air pressure in order to remove all oxidation or any other materials. The resulting level of wafer cleanliness allows better die attach of dice from the wafer
Test method
A definitive procedure for the identification, measurement and evaluation of a material, product, system, or service that produces a test result.
Standard cell
A small group of transistors that implement a logic function ; used as a building block to reduce the magnitude of a design task.
Accumulation condition
The region of the capacitance-voltage (C-V) curve for which a 5-V increment toward a more negative voltage for p-type material, or toward a more positive voltage for n-type material, results in a change of less than 1% in the maximum capacitance, Cmax (The "max" part of the abbreviation "Cmax"is written with subscript lowercase letters.)
Light Emitting Diode. a semiconductor device in which the energy of minority carriers in combining with holes is converted to light. Usually, but not necessarily, constructed as a P/N junction device.